The present invention concerns a self-aligned thin-film transistor (TFT) for a liquid crystal display (LCD) and a process for fabricating it, wherein the drain electrode and/or the source electrode is aligned with the gate electrode.
Generally, amorphous silicon TFT should have a high field effect current mobility and parasitic capacitances which are as low as possible, in order to be used for an active matrix liquid crystal display (AM-LCD). The field effect current mobility of a conventional amorphous silicon TFT is about 0.3 to 1.0 cm.sup.2 /V.sub.s, which is too small to design a large scale AM-LCD of high pixel density. If the channel width is increased to obtain a sufficient current, the area of the TFT is increased, so that the opening ratio for transmitting light through the LCD pixels is reduced.
Referring to FIGS. 1A and 1B, respectively illustrating cross-sectional views of a conventional channel-etch and etch-stopper TFT, parasitic capacitance will now be specifically described.
Deposited over a substrate 1 are a gate electrode 2, gate insulating layer 3, amorphous silicon semiconductor layer 4, channel protecting layer or etch stopper 5, contact layer 6, source electrode 7, and drain electrode 8. Generally the gate electrode 4 is overlapped by the source and drain electrodes to some extent. The overlapped length is indicated by .DELTA.L in FIGS. 1A and 1B of the drawings. This overlap causes, compared to an ordinary MOSFET, the TFT to produce considerable parasitic capacitances C.sub.gd (between gate and drain electrodes) and C.sub.gs (between gate and source electrodes). The C.sub.gd causes the voltage drop of the pixels as the gate voltage drops from a high state to a low state. This voltage drop is called the offset voltage or kick-back, and is approximately expressed by the following equation: ##EQU1##
When driving the liquid crystal by alternating current, the voltage applied to the pixels is reversed around the common voltage V.sub.com at every frame and in this case, the common voltage V.sub.com is lowered by the offset voltage .DELTA.V.sub.p so as to maintain a balance between the main frame and the subframe.
However, the liquid crystal capacitance C.sub.s is a function of the voltage, and therefore the balance is not precisely kept in the gray mode to produce a direct current thus resulting in flickering or persistence of images. Moreover, in order to reduce the difference of the offset voltages between gray modes and the absolute value of the offset voltage, the source capacitance C.sub.s is increased, which increases the opening ratio and the size of the TFT. To obviate this problem, conventionally there is provided an etch stopper TFT of half or wholly self-aligned type, as respectively shown in FIGS. 1C and 1D.